This invention relates to testing of memory modules, and more particularly to testing memory modules with error-correction code (ECC) memory.
Personal computers (PC's) and other electronic systems use small printed-circuit board (PCB) daughter cards known as memory modules. Memory modules are plugged into sockets on a motherboard, reducing a need to directly mount individual memory chips on the motherboard. The memory modules are built to meet specifications set by industry standards, thus ensuring a wide potential market and low cost.
Memory modules can be tested using general-purpose electronic-component testers, but these testers tend to be quite expensive. Memory modules can also be tested in PC-based testers. Since PC's are very inexpensive, test costs can be significantly reduced. The memory modules being tested can be inserted into memory module sockets on a PC motherboard, which executes a memory test program to test the memory modules. See as examples U.S. Pat. Nos. 6,178,526, 6,415,397, 6,357,023, and 6,351,827.
A drawback to using a PC motherboard for testing memory modules is that the memory module sockets can become worn with use, since thousands of different memory modules may be inserted and removed for testing. The standard memory module sockets on a PC motherboard are not designed for such frequent replacement of the memory modules. Specialized test sockets such as zero-insertion-force (ZIF) sockets may replace the standard memory module sockets on PC motherboards used as testers.
Another approach is to insert an extender card into the PC motherboard's memory module socket. The memory modules are then inserted into a test socket on the extender card for testing. A higher-quality test socket can be mounted on the extender card to receive the memory modules under test.
FIGS. 1A-B show an extender card between a PC motherboard and memory module being tested by the motherboard. In FIG. 1A, memory module 10 contains DRAM chips 18, 20. The number and arrangement of DRAM chips 18, 20 vary with the memory module design and size, and may be mounted on one or both sides of memory module 10.
Extender card 24 is a printed-circuit board (PCB) or other substrate that has test socket 22 mounted on its upper edge, and has metal fingers or contact pads along its bottom edge. Metal wiring traces on extender card 24 connect corresponding signals on the lower-edge contact pads to metal pads in test socket 22, thus passing signals through between PC motherboard 28 and memory module 10.
PC motherboard 28 is a larger PCB that has chips, sockets, and other components mounted thereon, such as chip 32 and expansion sockets 36 which have expansion cards 34 plugged in. Expansion cards 34 can be Peripheral Component Interconnect (PCI), AT-bus, or other expansion cards. Chip 32 can be the main microprocessor, chip set, cache memory, or other chips.
Memory module socket 26 is one of several sockets designed to fit memory module 10 or other memory modules. Memory module socket 26 is mounted to the PCB substrate of PC motherboard 28, and fits the contact pads on the bottom side of extender card 24, or the contact pads on memory module 10.
FIG. 1B shows the memory module and extender card plugged into the PC motherboard. The contact pads on memory module 10 fit into test socket 22 on extender card 24. Test socket 22 can be a zero-insertion force test socket while memory module socket 26 on PC motherboard 28 is an inexpensive socket. Test socket 22 can also be a conventional memory module socket similar to memory module socket 26. The contact pads on the bottom edge of extender card 24 fit into memory module socket 26 on PC motherboard 28. Electrical contact is made by sockets 22, 26, with wiring traces on extender card 24 passing most signals through from PC motherboard 28 to memory module 10.
During testing, different memory modules 10 are repeatedly inserted into test socket 22, tested by execution of a test program on PC motherboard 28, and removed from test socket 22 and placed in a passing or a failing bin. Extender card 24 remains inserted in test socket 22 while memory module 10 is repeatedly replaced.
FIGS. 2A-B show testing a memory module with an error-correction code (ECC) memory using an extender card. Some memories contain redundant bits of storage for error detection and/or error correction. For example, an 8-bit-wide memory can have one extra bit, called a parity bit, for detecting an error in the 8-bit word. Memory modules can have 9 bits of data, including the parity bit and 8 data bits.
With a single parity bit, errors can only be detected, not corrected. Having additional redundant bits allows for detection and correction of simple errors. The additional bits may also allow for detection but not correction of more complex errors.
As an example, a dual-inline memory module (DIMM) may contain 64 data bits and 8 ECC bits. Memory module 10 uses a total of nine 8-bit-wide DRAM chips. Eight DRAM chips 18 store the 64 data bits while one ECC DRAM chip 20 stores the 8 ECC bits. ECC DRAM chip 20 may be located in the middle of the eight DRAM chips 18, or in some other arrangement, and some of the DRAM chips may be mounted on the back side of memory module 10, or a second bank of chips may be mounted on the back side of memory module 10.
Metal contact pads 21 on the lower edge of memory module 10 are for inserting into test socket 22 on extender card 24. Metal wiring traces on extender card 24 connect signals from test socket 22 to the corresponding signals on lower-edge contact pads 25 so that all signals are passed through unchanged, as shown in FIG. 2B.
The direct pass-through of signals from lower-edge contact pads 25 to test socket 22 and contact pads 21 allows memory module 10 to be tested just as if memory module 10 were inserted directly into memory module socket 26 on PC motherboard 28. The increased height of test socket 22 above the surface of PC motherboard 28 makes testing easier since test socket 22 is more easily reached by an operator or handler machine.
During testing of memory module 10 inserted into test socket 22, DRAM controller 38 on PC motherboard 28 receives data from a CPU or bus master and generates control signals to DRAM chips 18, 20 on memory module 10 to write the data as 64-bit words. The 64 data bits are written to DRAM chips 18 on memory module 10 by DRAM controller 38, and the 64 data bits are also sent from DRAM controller 38 to ECC generator 30 on PC motherboard 28.
ECC generator 30 generates the 8 ECC bits that are the proper correction code for the 64 data bits. The 8 ECC bits are sent to ECC DRAM chip 20 through extender card 24 to be stored with the 64 data bits at the same address in the memory module.
When the address location is read back, the 64 data bits from DRAM chips 18 are again input to ECC generator 30, and the generated ECC code is compared with the 8 ECC bits read from ECC DRAM chip 20 on memory module 10. When the generated and read-back codes mis-match, error correction is attempted, or an error is signaled. An error could occur if the DRAM chips were not refreshed quickly enough, or due to a soft error such as an alpha-particle hitting a DRAM chip.
During testing of memory module 10, a variety of specialized data patterns may be written to DRAM chips 18 and read back. These specialized data patterns have been developed to detect certain types of errors that can occur in DRAM chips, such as a single memory cell that is stuck high or low, or shorts between adjacent cells. Patterns such as walking-ones, walking-zeros, checkerboard, and inverse checkerboards are often used.
FIG. 3 shows a checkerboard pattern stored in DRAM chips on a memory module. In this simplified example, only four data DRAM chips D1, D2, D3, D4 are shown and one ECC DRAM chip “ECC” in the five columns of the Figure. Each DRAM chip is only 4 bits wide in this simplified example.
A checkerboard pattern is written to each odd address, while an inverse-checkerboard pattern is written to each even address by a test program executing on the PC motherboard. This checkerboard pattern is useful for detecting a single memory cell that is shorted to a neighboring cell, since the neighboring cells all have the opposite data state. A cell in the “1” state is surrounded by 4 cells in the “0” state.
While the checkerboard pattern is properly written to the data DRAM chips 18, the ECC DRAM chip does not necessarily contain a checkerboard pattern. This is because the ECC DRAM chip is not written by the test program. Instead, ECC DRAM chip 20 is written by ECC code generated by ECC generator 30 on PC motherboard 28. The value of the ECC code is determined by the ECC coding function, which is a function of the data bits written to data DRAM chips 18. While a variety of ECC coding functions could be used, in general the ECC code does not look like the data pattern.
For example, the checkerboard pattern could produce the ECC value 0011 while the inverse checkerboard pattern produces an ECC value of 0001. Since the pattern of bits in ECC DRAM chip 20 is not a checkerboard, errors may be undetected in ECC DRAM chip 20.
A single memory cell in ECC DRAM chip 20 that is shorted to a neighboring cell may go undetected, since the neighboring cells do not all have the opposite data state. A cell in the “0” state might be surrounded by 1, 3, or 4 cells in the “0” state that could hide the error due to a short.
While memory modules with redundant storage are useful for error detection and correction, testing of such ECC memory modules can be problematic. A better testing procedure for use with ECC memory modules is desired. An extender card for testing ECC memory modules is also desired.